1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a method of manufacturing the same. More particularly, the present invention relates to a NAND-type flash memory, which includes a floating gate electrode and two or more gate oxide films having a different thickness in peripheral and cell sections.
2. Description of the Related Art
Recently, the development of a NAND-type flash memory has been made. The NAND-type flash memory is formed by gate pre-forming (or gate oxide film pre-forming) process. According to the gate pre-forming process, trench isolation is employed, and several gate oxide films having different thickness are separately formed.
However, in the NAND-type flash memory, gate oxide films 101a and 102a on a silicon (Si) substrate 103 are different in their thickness between a cell/Vcc section 101 and a Vpp section 102, as shown in FIG. 5A. For this reason, a step (a) is formed in the upper surface of SiN films (stopper SiN films) 101c and 102c on gate electrodes 101b and 102b. For example, the step (a) is a factor of causing the following disadvantage in shallow-trench isolation (STI) formation. As illustrated in FIG. 5B, a difference is made in the thickness of SiN films when the upper surface of a buried insulator 104 is removed by chemical mechanical polishing (CMP) using SiN films 101c and 102c as a stopper. More specifically, the SiN film 102c of the Vpp section 102 is thinner than the SiN film 101c of the cell/Vcc section 101. The excess thickness reduction of the SiN film 102c is a factor of reducing the a height (h) to the gate oxide film 102a. As a result, the gate oxide film 102a is easily damaged by etching (e.g., wet etching) after CMP. The gate oxide film 102a being damaged is a factor in causing failure such as gate leakage.
In particular, the NAND-type flash memory has a high-voltage row decoder circuit 111. As shown in FIG. 6, the row decoder circuit 111 is arranged in a peripheral region (corresponding to Vpp section 102) adjacent to a cell array region (Cell Array) 110 corresponding to the cell/Vcc section 101. Normally, the row decoder circuit 111 is formed using a gate oxide film for Vpp system (Vpp oxide film 102a). In other words, a high-voltage transistor exists in the row decoder circuit 111 of the NAND-type flash memory.
Conversely, a Vcc oxide film 101a is used, in general, in the cell array region 110, a guard ring 112 arranged between the cell array region 110 and the row decoder circuit 111 and a dummy AA pattern 113 near the row decoder circuit 111. For this reason, when a film to make a buried insulator 104 is subjected to CMP in STI formation, the SiN film 102c of the row decoder circuit 111 is excessively reduced in thickness as compared with the SiN film 101c. This is a factor in causing the foregoing failure.
In the conventional case, it is possible to readily realize the NAND-type flash memory having several gate oxide films of different thicknesses according to the gate pre-forming process. However, the stopper SiN film of the row decoder circuit is greatly reduced in thickness by CMP in the STI formation. As a result, the gate oxide film under the stopper SiN film is easily damaged; for this reason, there is a problem that failure such as gate leakage occurs.